Xin Zhang
Portrait of Xin Zhang

IBM T. J. Watson Research Center · Columbia University · New York, NY

Xin Zhang

Member of Technical Staff & Technical Lead, IBM T. J. Watson Research Center
Adjunct Professor of Electrical Engineering, Columbia University

Designing chips that power high‑performance computing
and quantum computing,
and
Building AI that designs chips.
96
papers
45+
US patents filed or granted
20+
ISSCC, JSSC & VLSI papers
7
ICML, NeurIPS & DAC papers

Xin Zhang is a Member of Technical Staff and Technical Lead at the IBM T. J. Watson Research Center in Yorktown Heights, NY, and an Adjunct Professor of Electrical Engineering at Columbia University. Xin's research spans AI for circuit design, power management integrated circuits, and power delivery, packaging and cooling for computing systems. At IBM, Xin has worked on 48 V power delivery for servers and datacenters, power management for IBM AI accelerators, and LLM-based analog circuit design, including projects with the MIT-IBM Watson AI Lab. Xin's most recent work is on superconducting quantum processors, including qubit and coupler physical design and simulation and the automation of the quantum chip design flow.

Before joining IBM in 2014, Xin was a scientist at the Institute of Microelectronics, A*STAR, Singapore; a project researcher and research assistant professor at the University of Tokyo; and a visiting scholar at the University of California, Berkeley.

Research

Theme 1

AI for chip design

Machine learning, and increasingly LLMs, that automate analog, power circuit design and manufacturing: language models that generate circuit topologies and optimize circuit sizing, reinforcement learning and tree search for topology synthesis, graph-transformer surrogate models for fast design evaluation, and ML that predicts circuit performance from schematic to layout to silicon.

Theme 2

Chips and circuits

Power management ICs for processors and AI accelerators: LDO regulators, buck converters, switched-capacitor and hybrid converters, 48 V-to-1 V conversion, and droop mitigation.

Most recently, superconducting quantum processors: qubit and coupler physical design and simulation, and quantum hardware design-flow automation.

Theme 3

Power, packaging and cooling

Delivering power and removing heat at the board, package and system level: 48 V power delivery for servers and datacenters, vertical and backside power delivery with integrated magnetics, heterogeneous integration of power converters, oscillating heat pipes and embedded cooling for high-heat-flux 3D packages, and thermally aware chiplet placement.

Selected highlights

Publications

Google Scholar →

AI for chip design 17 papers

2026
  1. LaMAGIC: Advanced Circuit Formulations for Language-Model-based Topology Generation for Analog Integrated Circuits
    C.-C. Chang, W.-H. Lin, Y. Shen, G. Zhou, Y. Chen, X. Zhang
    TODAESACM Transactions on Design Automation of Electronic Systems, 2026
  2. Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning
    H. Lu, S. Fan, S. Zhang, N. Cao, X. Zhang, J. Li
    TODAESACM Transactions on Design Automation of Electronic Systems, 2026
  3. HRL-Topo: Hierarchical Reinforcement Learning with Large Language Models for Analog Circuit Topology Synthesis
    P. Vijayaraghavan, L. Shi, E. Degan, V. Mukherjee, X. Zhang
    DACACM/IEEE Design Automation Conference (DAC), invited, 2026
  4. SLIC: Reinforcement Fine-Tuning Small LMs for Multi-Turn Analog Circuit Optimization
    Y. Xu, Z. Gao, C.-Y. Ko, Z.-W. Hong, W. Lu, T. Yu, X. Zhang, D. Boning, R. Han
    NeurIPSConference on Neural Information Processing Systems (NeurIPS), 2026
2025
  1. Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input
    D. V. Kochar, M. Ashok, J. Cohn, A. P. Chandrakasan, X. Zhang
    TCAS-IIEEE Transactions on Circuits and Systems I: Regular Papers, 2025
  2. Semiconductor SEM Image Defect Classification Using Supervised and Semi-Supervised Learning with Vision Transformers
    C.-F. F. Huang, K. Sieg, L. Karlinsky, N. Flores, R. Sheraw, X. Zhang
    ASMC36th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2025
  3. CircuitSynth-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
    P. Vijayaraghavan, L. Shi, E. Degan, V. Mukherjee, X. Zhang
    DACACM/IEEE Design Automation Conference (DAC), 2025
  4. LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
    D. V. Kochar, H. Wang, A. P. Chandrakasan, X. Zhang
    ICLADIEEE International Conference on LLM-Aided Design (ICLAD), 2025
  5. AutoCircuit-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
    P. Vijayaraghavan, L. Shi, E. Degan, V. Mukherjee, X. Zhang
    ICMLInternational Conference on Machine Learning (ICML), 2025
  6. LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
    C.-C. Chang, W.-H. Lin, Y. Shen, Y. Chen, X. Zhang
    ICMLInternational Conference on Machine Learning (ICML), 2025
  7. Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input Best Track Manuscript Recognition
    D. V. Kochar, M. Ashok, J. Cohn, A. P. Chandrakasan, X. Zhang
    ISCASIEEE International Symposium on Circuits and Systems (ISCAS), 2025
2024
  1. Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design
    S. Fan, H. Lu, S. Zhang, N. Cao, X. Zhang, J. Li
    DACProceedings of the 61st ACM/IEEE Design Automation Conference, 2024
  2. LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
    C.-C. Chang, Y. Shen, S. Fan, J. Li, S. Zhang, N. Cao, Y. Chen, X. Zhang
    ICMLInternational Conference on Machine Learning (ICML), 2024
  3. CircuitSynth: Leveraging Large Language Models for Circuit Topology Synthesis
    P. Vijayaraghavan, L. Shi, E. Degan, X. Zhang
    LADIEEE LLM Aided Design Workshop (LAD), 2024
  4. Enhancing Reasoning to Adapt Large Language Models for Domain-Specific Applications
    B. Wen, X. Zhang
    NeurIPSNeurIPS 2024 Workshop on Adaptive Foundation Models, 2024
2022
  1. Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search
    S. Fan, S. Zhang, J. Liu, N. Cao, X. Guo, J. Li, X. Zhang
    TODAESACM Transactions on Design Automation of Electronic Systems, 2022
2021
  1. From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning
    S. Fan, N. Cao, S. Zhang, J. Li, X. Guo, X. Zhang
    ICCADIEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021

Chips and circuits 68 papers

2026
  1. Design of a Wide-Loading-Range Cap-Less LDO With Enhanced Power Supply Rejection and Speed
    K. Wang, J. Tang, S. Y. Sim, X. Zhang, C. Huang
    TCAS-IIEEE Transactions on Circuits and Systems I: Regular Papers, 2026
  2. Steady-State and Small-Signal Analysis of High-Ratio Hybrid Buck Converters With Enhancement to State-Space-Averaging Methodology
    M. R. Khan, X. Liu, X. Zhang, C. Huang
    TCAS-IIEEE Transactions on Circuits and Systems I: Regular Papers, 2026
  3. A Single-Chip Laser Diode Driver with Built-In Frequency-Sweep Linearization for FMCW LiDAR
    W. Zhu, J. Jiang, X. Sun, Z. Li, T. Gu, X. Zhang, C. Huang
    ISSCCIEEE International Solid-State Circuits Conference (ISSCC), 2026
  4. Piggybacked SC-on-CSCR: A Modular On-Chip Switched-Capacitor Converter for 12-to-60V Input 1.8-to-5V Output Achieving 5.67mW/mm² Power Density and 71.5% Peak Efficiency
    Y. Yang, X. Zhang, S. Du
    ISSCCIEEE International Solid-State Circuits Conference (ISSCC), 2026
  5. Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS
    X. Chen, A. Liss, W. Covington, Q. Cao, Y. Li, K. Wei, R. Magod, M. Khellah, X. Zhang, J. Gu
    ISSCCIEEE International Solid-State Circuits Conference (ISSCC), 2026
  6. A 1-to-1050-mA DLDO with Rising-Edge Computational Control and Load-Dependent Feedback Achieving 46-mV/ns DVS Rate and 0.15-Ps FoM
    Y. Xu, R. Wan, M. Li, Z. Wang, S. Kim, R. K. Krihshnamurthy, X. Zhang, M. Seok
    VLSI Symp.IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2026
  7. VSIMO: A DC-DC SIMO-based Current Mismatch Compensator Supporting Per-Output Bidirectional Power Flow for Stacked Voltage Domains Achieving >82% System Efficiency under up to 360-mA Load Mismatch
    Y. Xu, S. A. A. Hossain, B. Zhu, S. Kim, R. K. Krihshnamurthy, X. Zhang, M. Seok
    VLSI Symp.IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2026
2025
  1. A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors
    X. Chen, J. Feng, A. Shoukry, X. Zhang, R. Magod, N. Desai, J. Gu
    JSSCIEEE Journal of Solid-State Circuits, 2025
  2. Digital In-Memory Compute for Machine Learning Applications With Input and Model Security
    M. Ashok, S. Maji, X. Zhang, J. Cohn, A. P. Chandrakasan
    JSSCIEEE Journal of Solid-State Circuits, 2025
  3. Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
    M. Kar, J. Silberman, S. Venkataramani, …, X. Zhang, …, P.-F. Lu, L. Chang
    JSSCIEEE Journal of Solid-State Circuits, 2025
  4. Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency
    Y. Xu, Z. Wang, R. Wan, S. Kim, M. Gong, R. Krishnamurthy, X. Zhang, M. Seok
    SSC-LIEEE Solid-State Circuits Letters, 2025
  5. A High Density Three-Level Quadratic Buck Hybrid Converter for 48V-to-PoL Conversion
    K. Wang, S. Y. Sim, Y. Q. Choong, X. Zhang, S. Pakala, C. Huang
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), 2025
  6. A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control
    Z. Wang, Y. Xu, S. Kim, N. Desai, M. Gong, R. Krishnamuthy, X. Zhang, M. Seok
    CICCIEEE Custom Integrated Circuits Conference (CICC), 2025
  7. A Multi-Level Power Management Architecture for Battery-Powered SPAD Drivers with Supply Intrinsic Quenching and 10-ns Dead Time
    W. Zhu, X. Sun, X. Zhang, C. Huang
    CICCIEEE Custom Integrated Circuits Conference (CICC), 2025
  8. A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131mW Output Power
    Q. Zhuang, J. Sun, B. Li, J. Lu, X. Zhang, Y. Shi, H. Qiu
    ISSCCIEEE International Solid-State Circuits Conference (ISSCC), 2025
  9. A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator
    A. G. Amer, M. Ashok, X. Zhang, J. Cohn, A. P. Chandrakasan
    VLSID38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2025
2024
  1. A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity
    L. Zhao, J. Tang, X. Zhang, K. Wei, R. Magod, C. Huang
    JSSCIEEE Journal of Solid-State Circuits, 2024
  2. A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail
    Z. Wang, M. Li, S. Kim, N. Desai, R. K. Krishnamurthy, X. Zhang, M. Seok
    JSSCIEEE Journal of Solid-State Circuits, 2024
  3. A 94.7% Efficiency Direct-Step-Down Switched-Tank-Based 48V to 1V-3.3V Hybrid Converter with Constant-Resonant-Time Closed-Loop Control
    S. Y. Sim, X. Zhang, J. Jiang, K. Wei, C. Huang
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), 2024
  4. A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
    M. Ashok, S. Maji, X. Zhang, J. Cohn, A. P. Chandrakasan
    CICCIEEE Custom Integrated Circuits Conference (CICC), 2024
  5. Online Reliability Estimation Technique for Ceramic Capacitors in a 24V-to-1V DC-DC Buck Converter
    Z. Wang, S. Kim, N. Desai, M. Khatua, R. K. Krishnamurthy, X. Zhang, M. Seok
    ECCEIEEE Energy Conversion Congress and Exposition (ECCE), 2024
  6. A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
    M. Kar, J. Silberman, S. Venkataramani, …, X. Zhang, …, P.-F. Lu, L. Chang
    ISSCCIEEE International Solid-State Circuits Conference (ISSCC), 2024
2023
  1. A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer
    M. Gong, H. Chen, X. Zhang, R. Jain, A. Raychowdhury
    JSSCIEEE Journal of Solid-State Circuits, 2023
  2. A GaN-Based Reconfigurable Series-Parallel Hybrid Converter Supporting 48/24/12V Input and 0.8-1.2V Output with 83.7/87.8/90.7% Peak Efficiency
    M. Gong, H. Chen, M. Chang, J.-H. Yoon, X. Zhang, R. Jain, A. Raychowdhury
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), 2023
  3. A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking
    X. Chen, A. Shoukry, T. Jia, X. Zhang, R. Magod, N. V. Desai, J. Gu
    CICCIEEE Custom Integrated Circuits Conference (CICC), 2023
  4. 93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming
    Z. Wang, M. Li, S. Kim, N. Desai, R. K. Krishnamurthy, O. Lazaro, A. Blanco, X. Zhang, M. Seok
    ESSCIRCESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023
  5. A Single-Inductor 4-Phase Hybrid Switched-Capacitor Topology for Integrated 48V-to-1V DC-DC Converters
    M. R. Khan, K. Wei, X. Zhang, C. Huang
    ISCASIEEE International Symposium on Circuits and Systems (ISCAS), 2023
  6. A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS
    A. Agrawal, M. Kar, K.-H. Kim, …, X. Zhang, …, K. Gopalakrishnan, L. Chang
    VLSI Symp.IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
  7. Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs
    X. Chen, J. Feng, A. Shoukry, X. Zhang, R. Magod, N. Desai, J. Gu
    VLSI Symp.IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
  1. A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
    S. K. Lee, A. Agrawal, J. Silberman, …, X. Zhang, …, K. Gopalakrishnan, L. Chang
    JSSCIEEE Journal of Solid-State Circuits, 2022
  2. Analytical Comparison of 3-Level 2-Phase and Double-Step-Down Topologies for Integrated High-Ratio DC-DC Converters in BCD and GaN Process
    M. R. Khan, X. Zhang, C. Huang
    ECCEIEEE Energy Conversion Congress and Exposition (ECCE), 2022
  3. A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion
    M. Gong, X. Zhang, A. Raychowdhury
    VLSI Symp.IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022
2021
  1. A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference
    A. N. Mazumder, J. Meng, H.-A. Rashid, U. Kallakuri, X. Zhang, J.-S. Seo, T. Mohsenin
    JETCASIEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2021
  2. RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference
    S. Venkataramani, V. Srinivasan, W. Wang, …, X. Zhang, …, L. Chang, K. Gopalakrishnan
    ISCAACM/IEEE International Symposium on Computer Architecture (ISCA), 2021
  3. A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
    A. Agrawal, S. K. Lee, J. Silberman, …, X. Zhang, …, L. Chang, K. Gopalakrishnan
    ISSCCIEEE International Solid- State Circuits Conference (ISSCC), 2021
2020
  1. An Integrated Programmable Gate Timing Control and Gate Driver Chip for A 48V-to-0.75V Active-Clamp Forward Converter Power Block
    D. Kim, Y. Yamauchi, X. Meng, …, M. Seok, X. Zhang
    ECCEIEEE Energy Conversion Congress and Exposition (ECCE), 2020
2019
  1. Fully Integrated GaN-on-Si Technology Targeting on-Chip 48V Input Power Conversion
    K.-T. Lee, X. Zhang, T. Takken, E. Leobandung, D. Sadana, D. Piedra, T. Palacios
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), industry session, 2019
2018
  1. Analytic model for power MOSFET turn-off switching loss under the effect of significant current diversion at fast switching events
    B. Nguyen, X. Zhang, A. Ferencz, T. Takken, R. Senger, P. Coteus
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), 2018
2015
  1. An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage
    J. Zhou, C. Wang, X. Liu, X. Zhang, M. Je
    TCAS-IIEEE Transactions on Circuits and Systems I: Regular Papers, 2015
2014
  1. Analog-assisted digital low dropout regulator with fast transient response and low output ripple
    K. Mori, Y. Okuma, X. Zhang, H. Fuketa, T. Sakurai, M. Takamiya
    JJAPJapanese Journal of Applied Physics, 2014
  2. A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS
    X. Zhang, P.-H. Chen, Y. Okuma, K. Ishida, Y. Ryu, K. Watanabe, T. Sakurai, M. Takamiya
    JSSCIEEE Journal of Solid-State Circuits, 2014
  3. A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications
    J. Lee, V. V. Kulkarni, C. K. Ho, …, X. Zhang, …, X. Liu, M. Je
    ISSCCIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014
2013
  1. A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector
    X. Zhang, Y. Okuma, P.-H. Chen, K. Ishida, Y. Ryu, K. Watanabe, T. Sakurai, M. Takamiya
    A-SSCCIEEE Asian Solid-State Circuits Conference (A-SSCC), 2013
  2. A fast and energy-efficient level shifter with wide shifting range from sub-threshold up to I/O voltage
    J. Zhou, C. Wang, X. Liu, X. Zhang, M. Je
    A-SSCCIEEE Asian Solid-State Circuits Conference (A-SSCC), 2013
  3. A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS
    X. Zhang, P.-H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, M. Takamiya
    ASP-DAC18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
  4. Analog-Assisted Digital Low Dropout Regulator (AAD-LDO) with 59% Faster Transient Response and 28% Ripple Reduction
    K. Mori, Y. Okuma, X. Zhang, H. Fuketa, T. Sakurai, M. Takamiya
    SSDMExtended Abstracts of the 2013 International Conference on Solid State Devices and Materials, 2013
  5. 0.5 V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS
    M. Nomura, A. Muramatsu, H. Takeno, …, X. Zhang, …, H. Shinohara, T. Sakurai
    VLSI Symp.IEEE Symposium on VLSI Circuits, 2013
2012
  1. An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection
    P.-H. Chen, X. Zhang, K. Ishida, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    JSSCIEEE Journal of Solid-State Circuits, 2012
  2. Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and ${\rm V}_{\rm TH}$-Tuned Oscillator With Fixed Charge Programming
    P.-H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    JSSCIEEE Journal of Solid-State Circuits, 2012
  3. A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation
    X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, K. Watanabe, T. Sakurai, M. Takamiya
    TCAS-IIIEEE Transactions on Circuits and Systems II: Express Briefs, 2012
  4. On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS
    X. Zhang, K. Ishida, H. Fuketa, M. Takamiya, T. Sakurai
    TVLSIIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
  5. A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester
    P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    ASP-DAC17th Asia and South Pacific Design Automation Conference, 2012
  6. A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW
    X. Zhang, P.-H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, M. Takamiya
    VLSI Symp.Symposium on VLSI Circuits (VLSIC), 2012
2011
  1. 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
    P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    IEICE Trans.IEICE Transactions on Electronics, 2011
  2. 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
    Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M. Takamiya, T. Sakurai
    IEICE Trans.IEICE Transactions on Electronics, 2011
  3. A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage
    X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, T. Sakurai, M. Takamiya
    IEICE Trans.IEICE Transactions on Electronics, 2011
  4. Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits
    Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu, A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara, T. Sakurai
    TCAS-IIIEEE Transactions on Circuits and Systems II: Express Briefs, 2011
  5. A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting
    P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    A-SSCCIEEE Asian Solid-State Circuits Conference 2011, 2011
  6. An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS
    X. Zhang, K. Ishida, M. Takamiya, T. Sakurai
    ASP-DAC16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011
  7. A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme
    P.-H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    ISSCCIEEE International Solid-State Circuits Conference, 2011
  8. A Voltage-Reference-Free Pulse Density Modulation (VRF-PDM) 1-V Input Switched-Capacitor 1/2 Voltage Converter with Output Voltage Trimming by Hot Carrier Injection
    X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, K. Watanabe, T. Sakurai, M. Takamiya
    VLSI Symp.IEEE Symposium on VLSI Circuits, 2011
2010
  1. A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction
    X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, K. Watanabe, T. Sakurai, M. Takamiya
    A-SSCCIEEE Asian Solid-State Circuits Conference, 2010
  2. 0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS
    P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, T. Sakurai
    CICCIEEE Custom Integrated Circuits Conference 2010, 2010
  3. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
    Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M. Takamiya, T. Sakurai
    CICCIEEE Custom Integrated Circuits Conference 2010, 2010
  4. Misleading energy and performance claims in sub/near threshold digital systems
    Y. Pu, X. Zhang, J. Huang, …, M. Takamiya, T. Sakurai
    ICCADIEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
2007
  1. A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs
    X. Zhang, D. Yu, S. Sheng
    ASICON7th International Conference on ASIC, 2007
  2. A Pipelined Interpolating Analog-to-Digital Converter with Reduced Nonlinearity Error
    X. Zhang, D. Yu, S. Sheng
    ICIEA2nd IEEE Conference on Industrial Electronics and Applications, 2007
2006
  1. A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs
    X. Zhang, D. Yu, S. Sheng
    APCCASAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006

Power, packaging and cooling 11 papers

2025
  1. DiffChip: Thermally Aware Chip Placement with Automatic Differentiation
    G. Romano, A. Jain, N. Dehmamy, C. Chi, X. Zhang
    ECTCIEEE 75th Electronic Components and Technology Conference (ECTC), 2025
  2. Topology Optimization for Embedded Cooling of Multiple and Transient Workloads in 3D Semiconductor Packages
    Z. Wu, A. R. Kidambi, Y.-T. Yang, C.-M. Hung, S. Tian, X. Zhang, J. A. Weibel, L. Pan
    ITherm24th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2025
2024
  1. Silicon-based microscale-oscillating heat pipes for high power and high heat flux operation
    Q. Qian, X. Zhang, S. Tian, B. Yao, J. A. Weibel, L. Pan
    APLApplied Physics Letters, 2024
  2. Circuits and magnetics co-design for ultra-thin vertical power delivery: A snapshot review
    Y. Elasser, H. Li, P. Wang, J. Baek, K. Radhakrishnan, S. Jiang, H. Gan, X. Zhang, D. Giuliano, M. Chen
    MRS Adv.MRS Advances, 2024
  3. Modeling of Backside Power Delivery and Thermal Management in Semiconductor Die Packages
    Z. Wu, X. Zhang, S. Tian, A. R. Kidambi, J. A. Weibel, L. Pan
    ITherm23rd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2024
2023
  1. Experimental Investigation of Ultra-Thin Microchannel Oscillating Heat Pipes with Submillimeter-Scale Thickness
    Q. Qian, X. Zhang, S. Tian, J. A. Weibel, L. Pan
    ITherm22nd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2023
2020
  1. A 12- or 48-V Input, 0.9-V Output Active-Clamp Forward Converter Power Block for Servers and Datacenters
    X. Zhang, B. Nguyen, A. Ferencz, T. Takken, R. Senger, P. Coteus
    TPELIEEE Transactions on Power Electronics, 2020
  2. Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers
    M. Gong, X. Zhang, A. Raychowdhury
    MWSCASIEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020
2019
  1. A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper)
    T. Takken, A. Ferencz, C.-S. Wu, L. McAuliffe, T. Jia, X. Zhang
    VLSI Symp.Symposium on VLSI Circuits, 2019
2017
  1. A 12V-to-0.9V active-clamp forward converter power block with planar transformer, standing slab inductor and direct edge solder to motherboard
    X. Zhang, A. Ferencz, T. Takken, B. Nguyen, P. Coteus
    APECIEEE Applied Power Electronics Conference and Exposition (APEC), 2017
2014
  1. Ultra-high-Q air-core slab inductors for on-chip power conversion
    N. Wang, D. Goren, E. O'Sullivan, X. Zhang, W. J. Gallagher, P. Herget, L. Chang
    IEDMIEEE International Electron Devices Meeting, 2014

Patents

Granted patents and published applications, with continuations grouped together.

Theme 1

AI for chip design 10

  • Circuit design with ensemble-based learningUS 2025/0068821 A1
  • Machine learning for circuit prediction for semiconductor migrationUS 2025/0252231 A1
  • Algorithmic circuit design automationUS 2024/0095435 A1
  • Thermal and performance managementUS 11,989,068
  • Transformer-based surrogate model module for electric circuit performance modelingUS 2024/0394508 A1
  • Media capture device with power saving and encryption features for partitioned neural networkWO 2022/105661 A1
  • Multi-modal deep learning based surrogate model for high-fidelity simulationUS 2021/0279386 A1
  • Analog circuit for Softmax functionUS 2020/0167402 A1
  • Argmax function analog circuitUS 2020/0110579 A1
  • Image sensor with analog sample and hold circuit control for analog neural networksUS 10,708,522

Theme 2

Chips and circuits 15

  • Inverting single-inductor multiple-output (SIMO) DC-DC convertersUS 2025/0132674 A1
  • Current consumption controllerUS 11,860,702
  • Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFSUS 11,687,148
  • Fully integrated multi-phase buck converter with coupled air core inductorsUS 11,114,944; US 10,505,456
  • Smart controller with phantom inductor current sensing for switched mode power suppliesUS 11,150,712
  • Supply voltage decoupling circuits for voltage droop mitigationUS 10,972,083
  • Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the sameUS 10,707,755
  • Coupled-inductor DC-DC power converterUS 10,186,949
  • Voltage control utilizing multiple PWM patternsUS 10,381,929; US 10,097,090
  • Power converter using near-load output capacitance, direct inductor contact, and/or remote current senseUS 9,831,783
  • Bias voltage generator for measurementCN 201141908
  • Non-overlap clock generator circuitCN 101488738
  • Simulation module for circuit noise of sigma-delta modulatorCN 101482890
  • Offset voltage trimming circuit for differential circuitJP 2011-129195
  • Switched-capacitor voltage converterJP 2011-025605

Theme 3

Power, packaging and cooling 16

  • Separable interface cable structure for high voltage under-module power inputUS 12,183,999
  • Broadside coupled coplanar inductorsUS 11,817,250
  • Power converter with co-packaged secondary field effect transistors (FETs)US 11,799,384
  • Vertical power delivery packaging structureUS 11,799,374
  • Semiconductor chip having one or more on-chip metal windings and enclosed by top and bottom chip-external ferromagnetic coresUS 11,367,557
  • Combined inductor and heat transfer deviceUS 11,056,413
  • Discrete magnetic shielding sheetUS 2021/0202400 A1
  • Flexible silicon nanowire electrodeUS 11,058,337
  • High switching frequency, low loss and small form factor fully integrated power stageUS 10,943,898; US 10,535,650
  • Integrated power amplifierUS 2021/0111192 A1
  • Peripheral end face attachment of exposed copper layers of a first printed circuit board to the surface of a second printed circuit board by surface mount assemblyUS 11,026,326; US 10,398,025
  • Semiconductor with chip-external magnetic coresUS 2021/0183560 A1
  • Ultra low parasitic inductance integrated cascode GaN devicesUS 10,991,722
  • Unified conductor to lower the resistance between a planar transformer and one or more inductorsUS 10,939,543
  • Electrical contacts on the sidewall of a circuit boardUS 10,587,060
  • Solder assembly of pins to the peripheral end face of a printed circuit boardUS 10,321,564

Teaching

ELEN E6340 · Columbia University · since 2021

Power Management Integrated Circuits

A graduate course on modern power management IC design: linear and digital LDO regulators, switch-mode DC-DC converters and their control and compensation, switched-capacitor converters, and converter modeling and simulation. Practical design trade-offs and recent advances are emphasized, and a design project is an integral part of the course.

Mentoring

Industry mentor or Ph.D. thesis committee member for more than 20 graduate students from MIT, Duke, Columbia, Northwestern, Georgia Tech, Iowa State and other universities.

NameThenMy RoleNow
A. YangM.S., MITIndustry mentor—
N. LeungUndergraduate, MITIndustry mentorNot graduated
X. ChenPh.D., Northwestern UniversityIndustry mentor, thesis committeeNot graduated
Y. XuPh.D., Columbia UniversityIndustry mentorNot graduated
G. ZhouPh.D., Duke UniversityIndustry mentor, thesis committeeNvidia
K. LeePostdoc, MITIndustry mentorRice University
Z. SongM.S., MITIndustry mentor—
C.-C. ChangPh.D., Duke UniversityIndustry mentorNvidia
D. KocharPh.D., MITIndustry mentor, summer internGoogle
D. YooM.S., Columbia UniversityIndustry mentorApple
M. AshokPh.D., MITIndustry mentorAnalog Devices
L. ZhaoPh.D., Iowa State UniversityIndustry mentorMonolithic Power Systems
S. FanPh.D., New Jersey Institute of TechnologyIndustry mentorQuantum Science Center of GBA
Z. WangPh.D., Columbia UniversityIndustry mentor, thesis committeeApple
I. TerpstraM.S., MITIndustry mentorMIT CLEAR Lab
A. ShoukryPh.D., Northwestern UniversityIndustry mentor—
R. KhanPh.D., Iowa State UniversityIndustry mentor—
S. ZhangPostdoc, IBMIndustry mentorNvidia
D. KimPh.D., Columbia UniversityIndustry mentor, thesis committeeApple
M. GongPh.D., Georgia TechIndustry mentorIntel
X. MengPh.D., HKUSTSummer intern—
Y. YamauchiPh.D., University of TokyoSummer internBroadcom
T. JiaPh.D., Northwestern UniversitySummer internPeking University
B. NguyenPh.D., Washington State UniversitySummer internEmpower Semiconductor

Invited talks

  1. 2026
    AI in Analog Circuit Design: Emerging Opportunities and Innovations Seminar, University of Southern California
  2. 2025
    Digital Twins in IC Design and Manufacturing: Old Dog — Fancier Tricks or a New Promising Approach Panel, TxACE Symposium, University of Texas at Dallas
  3. 2025
    AI in Analog Circuit Design: Emerging Trends and Innovations Seminar, University of Tokyo
  4. 2025
    AI-Based Algorithms in Analog Circuit Topology Generation and Beyond Workshop, IMS 2025, San Francisco
  5. 2025
    AI in Analog Circuit Design: Emerging Trends and Innovations Seminar, University of Virginia
  6. 2025
    AI in Analog Circuit Design: Emerging Trends and Innovations Seminar, Duke University
  7. 2024
    Generative AI for Microsystem Design: Possibility and Opportunity Panel, MTL Seminar Series, MIT
  8. 2019
    Power Converters for Servers and Data Centers Seminar, Columbia University

Contact

xz3110@columbia.edu
Department of Electrical Engineering, Columbia University, New York, NY
IBM T. J. Watson Research Center, Yorktown Heights, NY